This section is intended to introduce the reader to various aspects of art that may be related to the subject matter described and/or claimed below, and is believed to be helpful in providing the reader with background information to facilitate a better understanding of the present disclosure. It should be understood that these statements are to be read in this light, not as admissions of prior art.
The present disclosure relates generally to integrated circuit architecture and, more specifically, to the generation of internal clock signals in integrated circuit devices.
Advances in semiconductor technology in recent years have reduced the minimum feature sizes of semiconductor devices in integrated circuits. These advances have led to increases in functionality of large-scale integrated circuits for a given chip area. For example, a single modern integrated circuit can now contain over a billion transistors, and can carry out multiple complex functions. In addition, these reductions in device feature sizes, such as metal-oxide-semiconductor (MOS) transistor gates, also serve to increase the switching speed of those devices and the overall performance of the integrated circuit.
Internal operations in such large scale integrated circuits, particularly those involving digital logic, are typically clocked. Some integrated circuits receive an external timing reference, such as a crystal oscillator or an externally generated clock signal, from which other internal clock signals can be derived. Internal functions within the integrated circuit, such as those functions that are carried out within an external clock, are typically based on such internally-generated clock signals. For instance, internal clock signals may be used for input and output operations where synchronization with the external clock is beneficial. Examples of conventional internal clock generator circuits include oscillators, frequency synthesizers, and the like, along with associated frequency divider or clock multiplier functions. Examples of internal functions controlled by such internal clock signals include the timing of signals involved in accessing selected memory cells in a memory array in the integrated circuit. Different memory technologies (e.g., static random access memory (SRAM), non-volatile memory, read-only memory (ROM), dynamic RAM (DRAM), etc.) may be implemented in the same large scale integrated circuit and may require control signals with different timings.
As is known in the art, the electrical behavior of solid-state components, such as MOS transistors, can vary depending on certain parameters. Variations in the fabrication process, for example variations in MOS transistor gate width or threshold voltage, will be reflected in the electrical performance of transistors and other components. The operating conditions of the integrated circuit, including the power supply voltage and the operating temperature, also result in variations in electrical performance. Thus, the switching speed of transistors in an integrated circuit can vary with variations in fabrication process parameters, power supply voltage, and operating temperature (sometimes referred to as “PVT” variations).
For integrated circuits in which internal functions are clocked by internal clock signals, these variations in device performance can affect both internal clock generator circuits and the circuits controlled by those clock generator circuits. For instance, it has been observed that internal timing may vary, due to these causes, by as much as 100% between the fastest “corner” of the process, voltage, and temperature (i.e., the combination of process parameters, power supply voltage, and operating temperature meeting specification limits that results in the fastest transistor switching speed) and the slowest “corner”. While these PVT variations are important factors to consider in the design of an integrated circuit, the matching of device sizes and attributes in modern complementary MOS (CMOS) integrated circuits generally allow the various circuit functions within the same device to “track” one another over these variations in process, voltage, and temperature. In other words, the various delay and switching times within the same integrated circuit tend to track one another over variations in process, temperature, and voltage. This tracking among devices in the same integrated circuit provides robustness in the overall integrated circuit operation over these variations.
Ferroelectric memory is a type of non-volatile memory technology based on capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-versus-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in these capacitors after voltage has been removed from the capacitor plates, with the stored state corresponding to the polarization state of the ferroelectric material. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by placing capacitors above the transistor level between overlying levels of metal conductors. Accordingly, ferroelectric memory technology is now commonly used as a non-volatile solid state read/write random access memory in many electronic systems, particularly portable electronic devices and systems, and is commonly referred to as ferroelectric RAM or FRAM.
Various memory cell architectures including ferroelectric capacitors are known in the art, including a 1T-1C (one transistor, one capacitor) arrangement that is similar to conventional DRAM memory cells, 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states, and even larger cells, such as 6T FRAM cells. The state of a ferroelectric memory cell is read by interrogating the capacitance of the ferroelectric capacitors to discern its polarization state, specifically by detecting the polarization capacitance (i.e., charge storage) that occurs a voltage above a coercive voltage is applied. When the memory state is opposite that of the applied voltage, that voltage will cause the capacitor to change its polarization state, which appears as a relatively high capacitance. But when the memory state matches that of the applied voltage, that voltage exhibits little capacitance due to polarization since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored.
Unfortunately, it has been observed that the switching behavior of ferroelectric capacitor does not necessarily track that of conventional CMOS devices over variations in process, voltage, and temperature. For example, at low temperatures (e.g., −40° C.), it has been observed that the polarization charge of a ferroelectric capacitor is reduced because the coercive voltage of the ferroelectric material increases with decreasing temperature, which weakens the stored state. In addition, the time required to “extract” the polarization charge (i.e., read the memory state of the ferroelectric capacitor) increases with decreasing temperature. In other words, low temperature operation of ferroelectric memory results in a read signal that is both weaker and slower, as additional time is necessary to develop a data signal for detection by sense amplifiers in the memory. In contrast, lower temperatures tend to decrease switching times and propagation delays in CMOS circuits, including internal clock generators, sense amplifiers, and the like, which can actually result in faster and improved operation. One approach in addressing this mismatch between the faster operation of CMOS circuits and the slower response by the ferroelectric cells is to design additional delay in the sense operation to ensure functionality at cold operating temperature. However, this additional delay may further slow memory operation at higher temperatures, particularly at the high temperature corner at which CMOS circuits are already near their slowest, which can undesirably push out access and cycle times of the memory.